In recent years, video is required in more places. CMOS image sensors have become more and more popular in such applications as medical instruments, security cameras, mobile phones and automotive industry due to its low power consumption, high speed imaging and easy system integration with on-chip circuits. Among the ADC integration architectures in CMOS image sensors, the column-parallel ADC has become perhaps the most widely used architecture to improve frame rate, reduce power consumption and lower readout noise.
Column-parallel ADC architectures can be further characterized based on the type of ADC used. Types include a successive approximation ADC (SAR), a cyclic ADC and a single-slope ADC (SS). SAR ADCs need to include a DAC that occupies a large silicon area. Hence, this is not a good choice for many applications. Cyclic ADCs can run at ultrahigh-speed with the cost of very high power consumption. This becomes a more challenging design specification. SS ADCs have been widely applied in CMOS image sensors because they provide relatively high resolution with minimal area and low power consumption.
For SS ADCs to operate properly, a critical building block “ramp generator” should provide a stable reference to the ADCs. In order to reduce the readout noise, the ramping signal should be as low noise as possible and have good common mode rejection in terms of power and ground bouncing. Therefore, a low noise and differential architecture for ramp generator is very important for modern CMOS image sensors, which employ column-parallel architecture with SS ADCs.
However, one drawback of SS ADCs is their slow conversion speed when bit resolution is increased. In principle, a SS ADCs needs a conversion time of 2N−1 clock cycles, where N is the resolution. For example, to complete a 12-bit data conversion, it takes 4,095 clock cycles. Consequently, the row operation time must be longer than 4,095 clock cycles; therefore the frame rate will be low if the pixel array has many columns. CMOS imagers' signal-to-noise ratio is limited by quantum fluctuation of signal electrons. The quantum fluctuation follows Poisson statistics and is termed shot noise, and can be expressed asephs=sqrt(N)  (1)
where ephs is the shot noise expressed in rms noise electrons and N is the amount of electrons in the pixel. This shows how shot noise increases with increasing signal. Shot noise often dominates among various noise sources in the large input signal region.
If the quantization step is increased, and quantization noise is kept lower than shot noise, the imaging quality typically will not be affected. A rule of thumb is that quantization noise should be less than half of shot noise to avoid artifacts.
This means that we can complete an effective higher-resolution conversion with less steps and hence the frame rate will be increased, which requires the ramp generator for the SS ADCs to be accelerated.